MAX1434ECQ+D【PDF 4/22 页】IC ADC 10BIT 50MSPS 100-TQFP

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MAX1434

Detailed Description

The MAX1434 ADC features fully differential inputs, a

pipelined architecture, and digital error correction for

high-speed signal conversion. The ADC pipeline archi-

tecture moves the samples taken at the inputs through

the pipeline stages every half clock cycle. The convert-

ed digital results are serialized and sent through the

LVDS/SLVS output drivers. The total clock-cycle latency

from input to output is 6.5 clock cycles.

The MAX1434 offers eight separate fully differential chan-

nels with synchronized inputs and outputs. Configure the

outputs for binary or two’s complement with the T/B digital

input. Global power-down minimizes power consumption.

Input Circuit

Figure 1 displays a simplified diagram of the input T/H

circuits. In track mode, switches S1, S2a, S2b, S4a, S4b,

S5a, and S5b are closed. The fully differential circuits

sample the input signals onto the two capacitors (C2a

and C2b) through switches S4a and S4b. S2a and S2b

set the common mode for the operational transconduc-

tance amplifier (OTA), and open simultaneously with S1,

sampling the input waveform. Switches S4a, S4b, S5a,

and S5b are then opened before switches S3a and S3b

connect capacitors C1a and C1b to the output of the

amplifier and switch S4c is closed. The resulting differ-

ential voltages are held on capacitors C2a and C2b. The

amplifiers charge capacitors C1a and C1b to the same

values originally held on C2a and C2b. These values are

Octal, 10-Bit, 50Msps, 1.8V ADC

with Serial LVDS Outputs

______________________________________________________________________________________

LVDS/SLVS

OUTPUT

DRIVERS

PLL

CLOCK

CIRCUITRY

REFERENCE SYSTEM

IN0P

IN0N

IN1P

IN1N

IN7P

IN7N

CLK

REFADJ REFIO REFP REFN

OUT0P

OUT0N

OUT1P

OUT1N

OUT7P

OUT7N

OVDD

AVDD

GND

CVDD

PLL3

PLL1

PLL2

LVDSTEST

OUTPUT

CONTROL

MAX1434

T/H

10-BIT

PIPELINE

ADC

10:1

SERIALIZER

T/H

10-BIT

PIPELINE

ADC

10:1

SERIALIZER

FRAMEP

FRAMEN

CLKOUTP

CLKOUTN

T/H

10-BIT

PIPELINE

ADC

10:1

SERIALIZER

POWER

CONTROL

SLVS/LVDS

T/B

*ICMV = INPUT COMMON-MODE VOLTAGE (INTERNALLY GENERATED).

CMOUT

ICMV*

Functional Diagram

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